This invention relates to a pipeline AD-converter comprising a cascade of AD-converter stages, each having an analog input, a digital output and a synchronous ΣΔ modulator with an input coupled to said analog input and an output coupled to said digital output of the stage, each AD-converter stage of the cascade, except the last one, further comprising an error signal generator for generating a baseband error signal from the signal applied to said analog input and the signal derived from said digital output and for applying the baseband error signal to the analog input of the next AD-converter stage in the cascade, the pipeline AD-converter further comprising a digital signal reconstruction path receiving the digital outputs of the AD-converter stages and generating there from an error-reduced digital representation of the analog signal applied to the analog input of the first stage in the cascade. Such pipeline AD-converter is known from the article □A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping□ by Y. Matsuya et al. in IEEE Journal of Solid State Circuits, Vol. sc-22, no. 6, December 1987, pp. 921-929.
A synchronous ΣΔ modulator is a 1-bit AD-converter. This kind of AD-converters has the advantage of having no nonlinear distortion and consequently a potentially wide dynamic range. In practice the dynamic range is upper-limited only by the level of the supply voltage. However, these AD-converters have the drawback that the signal to noise ratio is rather poor, especially when the sample rate is relatively close to the Nyquist rate. This drawback can be overcome by choosing a high sampling ratio. For example, with audio signals having a bandwidth of 20 kHz, and a Nyquist rate of 44.1 kHz, an excellent signal to noise ratio is obtained with a sampling rate of 2.8 MHz, i.e. an oversampling ratio of 64. However, when the signal bandwidth is substantially larger, such as video signals with a baseband of 5 MHz and a Nyquist rate of 13.5 MHz, an oversampling ratio of 64 would mean a sampling ratio of 864 MHz, which is too cumbersome for present day semiconductor technology.
A pipeline of ΣΔ modulators may solve this problem. The sample rate may be relatively low, e.g. 108 MHz for a 5 MHz bandwidth signal, i.e. an oversampling ratio of 8. The error signal may be derived by a subtracter, which subtracts the analog input signal from the digital output of the ΣΔ modulator. The relatively large baseband error signal generated by the first stage of the pipeline is AD-converted in the second stage and the so digitized error signal is, in the digital reconstruction path, processed reciprocally with respect to the analog processing in the first stage and subsequently used to cancel the error signal of the first stage in the digital output signal. The smaller baseband error signal generated by the second stage is digitized in the third stage of the cascade and subsequently, after appropriate digital signal processing, used to cancel the second error in the digital output signal and so on. In this way an AD converter is obtained with a noise level that is smaller the more stages are used, while the advantages, which are inherent to the use of 1-bit AD converters, are maintained.
However, by the error generator of the prior art it appeared difficult to derive the baseband error with large precision. The large precision is required to obtain a full cancellation of the error in the digital reconstruction path. The more cancellation is desired, the higher the precision should be. A limited precision would result in residual errors, which cannot be cancelled by the proposed method. Therefore the degree of precision should be such that the difference between an ideally obtained baseband error and the practically obtained baseband error is at least an order of magnitude less than the baseband error itself. It has been found, that one of the reasons for the lack of precision is the appearance of a signal related component in the baseband error signal that can be larger than the noisy component. The maximum magnitude of the signal that can be applied to the second stage of the cascade before overloading this stage is therefore smaller as it could be if the signal related error component would have been removed. This is a pity because it is desirable to drive the second stage with a baseband error signal as large as possible in order to make the influence of the sampling noise of the second stage as small as possible. The higher this influence is, the more stages in the cascade are required to obtain the desired performance specification. The main reason that limits the precision is the subtraction itself. Ideally, one of the two inputs of the subtracter should be the noise free analog input signal and the other one should be the same signal plus error where the error is the sampling noise only and the result would be a subtraction which results in the generation of the sampling noise only. In practice it is difficult to construct the signal paths of the two inputs to the subtracter such that the two magnitudes of the signal components are the same. One reason for it is the different nature of these two signals: one is an analog signal by nature and the other one is a signal with a binary waveform. Usually voltage-to-current converters are used in the construction of subtracters. The transfer gain of such a voltage-to-current converter is quite different for analog waveforms and binary waveforms. The result of this is the generation of a baseband error signal with an undesirable signal related component. It is the object of the invention to substantially reduce the level of the input signal related component in the output of the error signal generators of the pipeline AD converter and the pipeline AD converter of the present invention is therefore characterized in that said error signal generator comprises an asynchronous ΣΔ modulator having an input connected to the analog input of the AD-converter stage, means for subtracting the signals from the outputs of the synchronous and the asynchronous ΣΔ modulators and means for low pass filtering the result of the subtraction and for applying the filtered signal as error signal to the analog input of the next AD-converter stage in the cascade.
Asynchronous ΣΔ modulators are known per se in the art, e.g. from IEEE Transactions on Circuits and Systems, pp. 907-914, vol. 44, no 11, November 1997. The structure of the asynchronous ΣΔ modulator may preferably be substantially equal (matched) to that of the synchronous ΣΔ modulator except in that a clock pulse controls the comparator of the latter and the comparator of the former does not. The output signal of the asynchronous ΣΔ modulator is a square wave the duty-cycle of which is linearly proportional to the input signal. In contradistinction with a synchronous ΣΔ modulator, the asynchronous ΣΔ modulator is not subject to quantization noise because all analog properties are maintained through the time-continuous character of the zero-crossings in the square-wave signal. Therefore the output signal of an ideal asynchronous modulator can be regarded as a true replica of the input signal i.e. the low-frequency part of the spectrum of the output signal is identical to the spectrum of the input signal. On the other hand, when the synchronous and the asynchronous ΣΔ modulators are not ideal but, apart from the clock synchronization of the former, matched to each other, then the input signal component in the output of the two modulators is substantially equal. Consequently, when, according to the invention the output signals of the two modulators are subtracted from each other and low pass filtered, then the input signal components of the modulators cancel against each other and only the quantization noise delivered by the synchronous ΣΔ modulator remains. Other advantages of the use of an asynchronous ΣΔ modulator are that, as with the synchronous modulator, the whole dynamic range of the asynchronous modulator as determined by the available supply voltages can be utilized without non-linear distortion problems and that, by the virtue of the switched nature of the asynchronous and synchronous signals, the required operations, such as adding and subtracting, can be executed with large precision.
A second reason why it is difficult to obtain a good precision is that there is a phase shift between the two input signals of the subtracter. This phase shift is caused by the sample delay from the synchronous SD modulator. Therefore, in order to further enhance the input signal component cancellation, the pipeline AD converter of the present invention is further characterized by delay means in the output of the asynchronous ΣΔ modulator for compensating the delay of the synchronous ΣΔ modulator.
The third reason that limits the precision is the transfer gain of the subtracter. Even in the case that there is an ideal magnitude matching of the two inputs to the subtracter there is a difficulty to establish the effective gain of the noise between input and output of the subtracter. This gain should be precisely known, because its inverse has to be implemented in the digital reconstruction path. It is by far not easy to design a subtracter with an accurately known transfer gain figure. In contradistinction to the digital filters, whose amplitude and frequency characteristics can be accurately preset, the characteristics of the analog filters cannot be accurately preset because these characteristics are highly dependent on the values of the integrated circuit-elements which are subject to large production spread. Therefore, in order to still further enhance the accuracy of operation, the AD converter according to the present invention may be characterized by said error signal generators comprising controlled stages for controlling the amplitude and frequency characteristics of the error signal generators and a regulator for controlling said controlled stages. Although the absolute values of the integrated circuit-elements are largely spreading and unknown, the relative spread between matched circuit-elements of the same structure in the same integrated circuit chip is much lower. This may advantageously be used in the pipeline AD converter of the present invention which may be further characterized in that the regulator comprises dummy controlled stages which are matched to the controlled stages of the error signal generators, means to control the amplitude and frequency characteristics of said dummy stages to predetermined values by control signals and means to apply these control signals to the controlled stages of the error signal generators in the cascade of AD-converter stages. A very reliable and simple regulator of this kind is characterized in that said dummy controlled stages are fed back to constitute an oscillator generating an oscillatory signal, that one control signal is derived from the amplitude of the oscillatory signal for controlling the gain of said controlled stages and that another control signal is derived from the frequency of the oscillatory signal for controlling the frequency characteristics of said controlled stages. This type of control relies upon the property that the gain of a properly oscillating circuit has exactly the value one for the oscillation signal, independent of its amplitude. The amplitude is used to generate a control signal for a variable gain stage to ensure proper oscillation. If, then, by a second control mechanism the frequency of the oscillation is set at a precisely know value, both the frequency and the gain is accurately set for one reference point in the frequency characteristic of the error generation and therewith the frequency characteristic as a whole.